All Research Sponsored By:Texas Instruments, Inc.

TMS320C6000 Memory Test
APPLICATION NOTE: This set of programs has been compiled to provide a way to verify the integrity of internal DSP memory and external system memory for all devices currently in the TMS320C6000 (C6000) family.
Posted: 27 Mar 2002 | Published: 01 Feb 2002


IEEE 1149.1 Use in Design for Verification and Testability at Texas Instruments
WHITE PAPER: This document introduces those products that include ASIC cells, standard interface ICs, a bus master IC, a controller interface board for IBM compatibles, a high-speed scan interface, and software to control the scan bus.
Posted: 17 Mar 2002 | Published: 05 May 2000


Design-for-Test Analysis of a Buffered SDRAM DIMM
WHITE PAPER: This document presents a design-for-test analysis of a buffered synchronous dynamic random access memory dual in-line memory module.
Posted: 11 Mar 2002 | Published: 13 Aug 1996


Built-in Self-test (BIST) Using Boundary Scan
WHITE PAPER: This document shows how existing architectures can be modified to conform to IEEE 1149.1 architecture.
Posted: 09 May 2000 | Published: 01 Dec 1996


FIFO Solutions for Increasing Clock Rates and Data Widths
WHITE PAPER: Steady increases in microprocessor operating frequencies and bus widths over recent years have challenged system designers to find FIFO memories that meet their needs.
Posted: 13 Apr 2000 | Published: 01 Jan 1996