sponsored by Texas Instruments, Inc.
Posted:  11 Mar 2002
Published:  13 Aug 1996
Format:  PDF
Length:  15  Page(s)
Type:  White Paper
Language:  English
This document presents a design-for-test (DFT) analysis of a buffered synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM). The analysis is restricted to board-level manufacturing faults. The test problem is defined with a solution presented. Alternate methods are given. A comparative study contrasting a DFT approach using a boundary-scan test vs. a non-DFT approach is presented.


Sri Jandhyala
Texas Instruments, Semiconductor Group

Adam Ley
Texas Instruments, Semiconductor Group

Circuit Design | DRAM | Integrated Circuit Test Equipment | RAM | Testing

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