Higher data-transfer rates have dictated the need for FIFOs to evolve into clocked architecture wherein data is moved in and out of the device with synchronous controls. Each synchronous control of the clocked FIFO uses enable signals that synchronize the data exchange to a free-running (continuous) clock. Since the continuous clocks on each port of a clocked FIFO can operate asynchronously to each other, internal status signals indicating when the FIFO is empty or full can change with respect to either clock. To use a status signal for port control, it is synchronized to the port's clock on a clocked FIFO. Synchronization of these signals with flip-flops introduces metastability failures that increase with clock frequency. TI uses two-stage flag synchronization to greatly improve reliability. Higher clock frequencies augment raw speed, but greater bandwidth is also achieved by increasing the data width. Wider datapaths can have the associated cost of large board area due to increased package sizes. New compact packages for TI's FIFOs reduce this cost.