The reuse of many hardware IP blocks in a mix-and-match style suggests reuse of the verification components as well. At eInfochips, when we develop the Verification Components, we leverage our rich experience in ASIC/SoC design verification and expertise on the high-level verification languages(HVLs).

The verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. These verification solutions reduce the time to create the verification infrastructure and automated test bench environment required for verifying today's DSM designs and complex SoCs.